Modern integrated circuit designs have become extremely complex. As a result, various techniques have been developed to verify that circuit designs will operate as desired before they are implemented in an expensive manufacturing process. For example, logic simulation is a tool used for verifying the logical correctness of a hardware design. Designing hardware today involves writing a program in the hardware description language. A simulation may be performed by running that program. If the program (or model) runs correctly, then one can be reasonably assured that the logic of the design is correct at least for the cases tested in the simulation.
Software-based simulation, however, may be too slow for large complex designs such as SoC (System on Chip) designs. Although design reuse, intellectual property, and high-performance tools all can help to shorten SoC design time, they do not diminish the system verification bottleneck, which consumes 60-70% of the design cycle. Hardware emulation provides an effective way to increase verification productivity, speed up time-to-market, and deliver greater confidence in final products. In hardware emulation, a portion of a circuit design or the entire circuit design is emulated with an emulation circuit or “emulator.”
Two categories of emulators have been developed. The first category is programmable logic or FPGA (field programmable gate array)-based. In an FPGA-based architecture, each chip has a network of prewired blocks of look-up tables and coupled flip-flops. A look-up table can be programmed to be a Boolean function, and each of the look-up tables can be programmed to connect or bypass the associated flip-flop(s). Look-up tables with connected flip-flops act as finite-state machines, while look-up tables with bypassed flip-flops operate as combinational logic. The look-up tables can be programmed to mimic any combinational logic of a predetermined number of inputs and outputs. To emulate a circuit design, the circuit design is first compiled and mapped to an array of interconnected FPGA chips. The compiler usually needs to partition the circuit design into pieces (sub-circuits) such that each fits into an FPGA chip. The sub-circuits are then synthesized into the look-up tables (that is, generating the contents in the look-up tables such that the look-up tables together produce the function of the sub-circuits). Subsequently, place and route is performed on the FPGA chips in a way that preserves the connectivity in the original circuit design. The programmable logic chips employed by an emulator may be commercial FPGA chips or custom-designed emulation chips containing programmable logic blocks.
The second category of emulators is processor-based: an array of Boolean processors able to share data with one another is employed to map a circuit design, and Boolean operations are scheduled and performed accordingly. Similar to the FPGA-based, the circuit design needs to be partitioned into sub-circuits first so that the code for each sub-circuit fits the instruction memory of a processor. Whether FPGA-based or processor-based, an emulator performs circuit verification in parallel since the entire circuit design executes simultaneously as it will in a real device. By contrast, a simulator performs circuit verification by executing the hardware description code serially. The different styles of execution can lead to orders of magnitude differences in execution time.
While executing like a real device, an emulator's running speed is much lower, usually no more than a few mega-hertz. Clock generation and distribution can have a significant impact on the performance of an emulator, especially considering SoC designs of today. The SoC designs of today are becoming extremely complex with an increasing number of clocks, synchronous and asynchronous. The primary drivers of the large number of asynchronous clocks are IP (intellectual property) blocks from different vendors, different bus protocols, different power modes, and increased interfaces and peripheral devices. Power consumption has also become one of the major limiting factors in current electronic system. To reduce power consumption, an SoC design typically does not keep all the clock domains active all the time. Even in an active clock domain, clock-gating may dynamically shut off the clock to portions of the clock domain that are “idle” for some cycles. It is also common practice to choose one clock amongst two or more clocks through multiplexing logic. At any given instant of time, only one of the two or more clocks is activated. The existence of inactive clocks, either by clock gating or by selection through multiplexing, allows an emulator user to control the clock generator in the emulator so that the fastest clock signals generated may be used for the fastest active clocks. While improving the emulator performance, this approach is “manual” in nature and executes through executing time-consuming software codes. It is desirable to develop a scheme for automatic control of clock generation.